PLDs may be used to implement large systems that include millions of gates and megabits of embedded memory. Of the tasks required in managing and optimizing design, placement of logical components on the PLDs and routing connections between logical components on the PLD utilizing available resources can be the most challenging and time consuming. In order to satisfy timing and placement specifications, several iterations are often required to determine how logical components are to be placed on the target device and which routing resources to allocate to the logical components.
The complexity of large systems often requires the use of EDA tools to manage and optimize their design onto physical target devices. Automated placement and routing algorithms in EDA tools perform the time consuming task of placement and routing of logical components onto physical devices. However, even state of the art automated placement and routing algorithms are sometimes incapable of producing solutions that are comparable to user defined manual placement. User defined manual placement techniques may be able to identify critical sections of logic that should be grouped together in order to satisfy timing constraints that automated placement algorithms are slow to or even unable to identify. Similarly, user defined manual routing techniques may be able to identify efficient routing strategies that automated routing algorithms may have difficulties recognizing.
In order to leverage user-knowledge into the automated placement and routing process, some EDA tools allow users to provide input such as user-specified constraints into its automated placement and routing algorithms. The drawbacks of these functions are that these EDA tools invite users to over-constrain which makes the placement and routing procedure less efficient. In the worse cases, over-constraining may result in placement and routing failures or poor performance of systems.
Thus, what is needed is a method and apparatus for leveraging user specified constraints in the design process only when those constraints are helpful in the placement and routing of logical components.